There is ongoing pressure to make memory cells such as static RAM (SRAM) cells smaller. As process technologies shrink into deep-submicron (e.g. 65 nm, 45 nm and 32 nm), the manufacturability of these tiny SRAM cells becomes far harder. In large part, this is due to the photolithography patterns being increasingly difficult to define accurately on the wafer.
Manufacturable SRAM cells must be as small as possible whilst maintaining tight control over their device parameters in order to guarantee operation across the full product specification. Sometimes it is necessary to use larger transistors in an SRAM cell in order to keep the manufacturing variation within acceptable limits: so there is a trade-off between cell area and device variability.
A technique that reduces the manufacturing variability of devices in an SRAM cell would be desirable, as it would enable a wider product operating range and/or a smaller cell area.
A typical SRAM memory device is now described with reference to FIG. 1. The device comprises an N by M array 12 of memory cells 14, with N columns and M rows where N and M are any integer. A plurality (M) of bit lines BL1 . . . BLM and a plurality (N) of word lines WL1 . . . WLN are formed in the device. Within each row, each cell 14 is connected to a bit line BL of the respective row. Within each column, each cell 14 is connected to a word line WL of the respective column.
The bit lines BL and world lines WL are connected to addressing, reading and writing logic (not shown) as known in the art. For each bit line BL, there may also be formed a respective corresponding inverse bit line BL (not shown), which is not strictly necessary but improves tolerance to noise.
In operation, access to a cell 14 is enabled by asserting its corresponding word line WL (only one word line WL is asserted at any one time). In a read cycle, this allows the stored binary value of each cell 14 of that word line WL to be read from each of the respective bit lines BL1 . . . BLM. In a write cycle, this allows a binary value to be stored in each cell 14 of that word line WL by driving that value onto each of the respective bit lines BL1 . . . BLM. In standby state, no word line WL is asserted and each cell 14 simply stores its respective value.
FIG. 2 is a circuit diagram showing two conventional memory cells 14n and 14n+1 as might typically be formed in part of the array 12, the cells 14n and 14n+1 being on adjacent word lines WLn and WLn+1 respectively on the same bit line BL. Each cell 14 of this example is a CMOS “6T” (six transistor) SRAM cell, formed comprising a first transistor 1 and a second transistor 2 connected together as a cross-coupled pair, a third transistor 3 and a fourth transistor 4 connected together as another cross-coupled pair, and a fifth transistor 5 and a sixth transistor 6 each connected as an access transistor. The first and third transistors 1 and 3 together form an inverter, and the second and fourth transistors 2 and 4 together form another inverter, and the two inverters may also be described as cross-coupled. Each row of cells 14 is formed with both bit line BL and its inverse BL. A memory cell arrangement of this type is known in the art.
As shown, a first terminal of the first transistor 1 is connected to a supply 9, a first terminal of the second transistor is connected to the supply 9, the control terminal of the first transistor 1 is connected to a second terminal of the second transistor 2, and the control terminal of the second transistor 2 is connected to a second terminal of the first transistor. A first terminal of the third transistor is connected to ground 10, a first terminal of the fourth transistor 4 is connected to ground 10, the control terminal of the third transistor 3 is connected to a second terminal of the fourth transistor 4, and the control terminal of the fourth transistor 4 is connected to a second terminal of the third transistor 3. The second terminal of the first transistor 1 is connected to the second terminal of the third transistor 3, and the second terminal of the second transistor 2 is connected to the second terminal of the fourth transistor 4. A second terminal of the fifth transistor 5 is connected to the bit line BL, a first terminal of the fifth transistor 5 is connected to the second terminal of the third transistor 3 and the control terminal of the second transistor 2, and the control terminal of the fifth transistor 5 is connected to the nth word line WLn. A second terminal of the sixth transistor 6 is connected to the inverse bit line BL, a first terminal of the sixth transistor 6 is connected to the second terminal of the fourth transistor 4 and the control terminal of the first transistor 1, and the control terminal of the sixth transistor 6 is connected to the nth word line WLn.
In the case where the transistors are MOSFETs (Metal Oxide Field Effect Transistors), the control terminal of each is the gate, the first terminal of each is the source, and the second terminal of each is the drain. In the illustrated example, the first and second transistors 1 and 2 are PMOS transistors (p-type MOSFETs); and the third, fourth, fifth and sixth transistors 3, 4, 5 and 6 are NMOS transistors (n-type MOSFETS); n-type being the opposite of p-type.
The structure of the adjacent cell 14n+1 is substantially the same, but with the second terminal corresponding to that of the fifth transistor 5 connected to the inverse bit line BL, the second terminal corresponding to that of the sixth transistor 6 connected to the bit line BL, and the control terminals corresponding to those of the fifth and sixth transistors 5 and 6 connected to the n+1th word line WLn+1. The pattern is repeated alternately across each bit line BL for as many bits as are required in a word, and for as many words as are required.
In operation, each cell 14 has only two possible steady states. In a write cycle, the write line signal is asserted at the control terminals of the fifth and sixth transistors 5 and 6 such that they each turn on, i.e. each conduct to form an electrical connection between their respective first and second terminals. A binary value is then driven onto the bit line BL and the inverse of the value is driven onto the inverse bit line BL. Then, depending on that value, the cell adopts one of the two steady states. That is, either the first and fourth transistors 1 and 4 turn on (i.e. conduct between their respective first and second terminals) whilst the second and third transistors 2 and 3 turn off (i.e. do not conduct between their respective first and terminals), such that the node 11 between the first and third transistors 1 and 3 is forced up to the supply voltage 9 and the node 13 between the second and fourth transistors 2 and 4 is forced down to the ground 10; or vice versa. Note that the bit line input-drivers (not shown) are strong enough to override the previous state of the cross-coupled inverters.
When the write cycle is ended, the write line signal is de-asserted and the cell retains whichever of these two steady states it was driven into. In a read cycle, the word line signal is again asserted at the control terminals of the fifth and sixth transistors 5 and 6, and the corresponding value will appear on the bit line BL (and its inverse on the inverse bit line BL) depending on which steady state the cell was left in.
FIG. 3 is a partial plan view of an example integrated circuit (IC) package containing the memory device of FIGS. 1 and 2, showing a portion of the layout of the array 12 (not necessarily to scale). FIG. 4 is a cross section through line A of FIG. 3.
The package comprises active areas 16, shown here schematically as the dotted areas, these being the areas of silicon in which p-n junction devices such as MOSFETs and/or other transistors are formed. The term “active area” will be understood by a person skilled in the art. The package also comprises interconnects 17, shown here schematically as the cross-hatched areas, which are preferably polysilicon and form conducting connections within the illustrated layer of the package (in the plane of the page). The package also comprises vertical interconnects 15, shown here schematically as crossed squares, which form vertical conducting connections (perpendicular to the page) to a metalisation layer which connects between other such interconnects 15. The metallisation layer is not shown here, but the connections for a conventional memory cell will be known to a person skilled in the art. The package also comprises insulating mask areas 18, shown here schematically as the blank areas within the illustrated portion, which are preferably silicon oxide and act to mask against doping when the devices are formed in the active areas 16. An individual cell 14 is marked out for the purpose of illustration with a dotted line. It will be appreciated by a person skilled in the art that the pattern for a cell 14 repeats or tessellates over a wider area than is illustrated to form an array of such cells.
In the illustrated example, the third, fourth, fifth and sixth transistors 4, 5, 6 and 7 are NMOS devices formed in a first area of active area silicon 16 comprising upper and lower portions 20 and 23; and the first and second transistors 1 and 2 are PMOS devices formed in a second area of active area silicon 16 comprising central portions 21 and 22. The exact details of which transistors are formed where and how they are connected by the metalisation layer are not discussed in detail here, but CMOS memory cells are well known and these details will be apparent to a person skilled in the art.
In manufacture, the layout of FIG. 3 is built up as follows. First is provided a silicon substrate 26, in this case p-type, on which a layer of silicon oxide 18 is formed. Portions of this oxide 18 are etched away by photolithography to form the required pattern, i.e. to expose the areas where devices will be formed.
A PMOS transistor has an n-type channel and a p-type source and drain, formed by adding p-type dopant to an n-type foundation. Accordingly, since the substrate in this example is p-type, n-wells 27 are then formed in the central portions 21 and 22 of the active area 16 to provide an n-type foundation in which PMOS transistors can be formed. Conversely, an NMOS transistor has a p-type channel and an n-type source and drain, formed by adding n-type dopant to a p-type foundation. The substrate in this case is already p-type, no well is required in the upper and lower portions 20 and 23 of the active area 16.
Next, the polysilicon interconnects 17 are laid down. Then p-type dopant 28 is added to the central portions 20 and 21 of the active areas 16 where the PMOS transistors are formed, and n-type dopant is added to the upper and lower portions 20 and 23 where the NMOS transistors are formed. The combination of the remaining oxide 18 and the polysilicon interconnects 17 act as a mask for this doping stage (referred to in the art as “self aligned source drain doping”). These newly doped areas form the sources and drains of the transistors, upon which vertical interconnects 15 to the metalisation layer are laid. Wherever a polysilicon interconnect 17 crosses the active area 16, a gate is formed, and the doped areas either side of that interconnect 17 form the corresponding source and drain (the devices is symmetric so that either terminal can be the source or drain).
Finally, further insulation (not shown) is added to cover the exposed silicon of the active areas 16, the metalisation layers (also not shown) are formed, and the device is packaged into an integrated circuit package.
Note that the figures are somewhat schematic, especially with reference to FIG. 4 in that a thin insulating layer (not shown) of oxide 18 is actually left beneath the interconnects 17 in the regions of active area 16 where they cross to form a gate, as will be familiar to a person skilled in the art. The heights of the various illustrated elements in FIG. 4 are also not necessarily to scale. Further, note that in the above manufacturing process, a number of additional stages of masking will be required (e.g. when forming the n-wells), which again will be familiar to a person skilled in the art and for brevity are not described herein.
This layout topology is referred to as “split bit line” because the connections to the bit lines are made at opposite sides of the memory cell (e.g. top and bottom active area stripes 20 and 23). This topology is widely known in the prior art. There are other cell topologies which can also be used to realise the same circuit, however they have fallen out of favour since the end of the last millennium.
The PMOS devices 1 and 2 form a series of rectangular shapes 29 in the active area regions 21 and 22 interspersed by separating gaps 19 where the oxide 18 remains, and the NMOS devices 3, 4, 5 and 6 form two continuous strips 20 and 23 of active area 16. The gaps 19 provide electrical isolation to ensure there is no electrical interaction between cells 14. The gaps 19 also provide space for a polysilicon interconnects 17 to reach the opposite side of a cell 14 to create the described cross coupling.
As discussed, it would be advantageous to reduce the manufacturing variability of these and other types of memory arrays.